18675257. MEMORY SYSTEM AND MEMORY DEVICE simplified abstract (Kioxia Corporation)

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MEMORY SYSTEM AND MEMORY DEVICE

Organization Name

Kioxia Corporation

Inventor(s)

Naomi Takeda of Yokohama (JP)

Masanobu Shirakawa of Chigasaki (JP)

Akio Sugahara of Yokohama (JP)

MEMORY SYSTEM AND MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18675257 titled 'MEMORY SYSTEM AND MEMORY DEVICE

Simplified Explanation

The patent application describes a memory system that can store and write data in a specific manner.

  • Memory system with n memory cells, each capable of storing j bits of data
  • Controller writes portions of data from consecutive logical addresses to memory cells one by one
  • Data is written in ascending order of logical addresses
  • Each portion of data is written as a specific bit of the total bits stored in each memory cell

Key Features and Innovation

  • Efficient writing of data to memory cells in a specific order
  • Utilizes logical addresses to organize data storage
  • Maximizes storage capacity by writing data in a structured manner

Potential Applications

  • Computer memory systems
  • Data storage devices
  • Embedded systems

Problems Solved

  • Efficient data organization in memory systems
  • Optimized use of memory cell capacity
  • Streamlined data writing process

Benefits

  • Increased data storage efficiency
  • Improved data retrieval speed
  • Enhanced memory system performance

Commercial Applications

Memory system manufacturers can utilize this technology to create more efficient and high-performance memory products for various applications in the market.

Questions about Memory Systems

1. How does this memory system improve data storage efficiency? 2. What are the potential applications of this technology in the computer industry?

Frequently Updated Research

Stay updated on the latest advancements in memory system technology to ensure optimal performance and efficiency in data storage solutions.


Original Abstract Submitted

According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.