18664483. INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Shang-Yun Hou of Jubei (TW)

Sung-Hui Huang of Dongshan Township (TW)

Kuan-Yu Huang of Taipei (TW)

Hsien-Pin Hu of Zhubei (TW)

Yushun Lin of Taipei City (TW)

Heh-Chang Huang of Hsinchu (TW)

Hsing-Kuo Hsia of Jhubei (TW)

Chih-Chieh Hung of Hsinchu (TW)

Ying-Ching Shih of Hsinchu (TW)

Chin-Fu Kao of Taipei (TW)

Wen-Hsin Wei of Hsinchu (TW)

Li-Chung Kuo of Taipei (TW)

Chi-Hsi Wu of Hsinchu (TW)

Chen-Hua Yu of Hsinchu (TW)

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18664483 titled 'INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME

The abstract describes a method of forming an integrated circuit package, which involves attaching an integrated circuit die to a substrate, forming a dummy die, attaching the dummy die adjacent to the integrated circuit die, and encapsulating the structure with an encapsulant. The encapsulant, dummy die, and integrated circuit die are then planarized to create a level surface. The interior portion of the dummy die is removed, leaving behind an annular structure.

• Integrated circuit package formation method
• Attachment of integrated circuit die to substrate
• Formation of dummy die
• Encapsulation of structure with encapsulant
• Planarization of encapsulant, dummy die, and integrated circuit die
• Removal of interior portion of dummy die
• Remaining portion of dummy die forms annular structure

Potential Applications: - Semiconductor industry for packaging integrated circuits - Electronics manufacturing for compact and efficient devices

Problems Solved: - Ensures proper encapsulation and planarization of integrated circuit packages - Provides a method for forming annular structures in integrated circuit packages

Benefits: - Improved reliability and performance of integrated circuit packages - Enhanced structural integrity and thermal management

Commercial Applications: Title: Advanced Integrated Circuit Packaging Method This technology can be utilized in the semiconductor industry for manufacturing high-performance electronic devices with compact and reliable integrated circuit packages. The method offers improved encapsulation and planarization techniques, leading to enhanced device performance and longevity in various electronic applications.

Prior Art: Researchers can explore existing patents related to integrated circuit packaging methods, planarization techniques, and semiconductor device manufacturing processes to understand the evolution of this technology.

Frequently Updated Research: Researchers in the field of semiconductor packaging and microelectronics may conduct studies on novel materials for encapsulation, advanced planarization methods, and optimization of integrated circuit package designs for improved performance and reliability.

Questions about Integrated Circuit Packaging Method: 1. How does the planarization process impact the overall performance of integrated circuit packages? The planarization process ensures a level surface for the encapsulated integrated circuit die, improving thermal dissipation and structural integrity of the package.

2. What are the key considerations for selecting materials for encapsulation in integrated circuit packaging? The selection of materials for encapsulation in integrated circuit packaging depends on factors such as thermal conductivity, adhesion properties, and compatibility with the integrated circuit die to ensure proper functioning and reliability of the package.

Original Abstract Submitted

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.