18661700. METHOD OF FABRICATING PACKAGE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

METHOD OF FABRICATING PACKAGE STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chih-Hsuan Tai of Taipei City (TW)

Hao-Yi Tsai of Hsinchu City (TW)

Yu-Chih Huang of Hsinchu (TW)

Chia-Hung Liu of Hsinchu City (TW)

Ting-Ting Kuo of Hsinchu City (TW)

Ban-Li Wu of Hsinchu City (TW)

Ying-Cheng Tseng of Tainan City (TW)

Chi-Hui Lai of Taichung City (TW)

METHOD OF FABRICATING PACKAGE STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18661700 titled 'METHOD OF FABRICATING PACKAGE STRUCTURE

Simplified Explanation

The patent application describes a package structure for a semiconductor device, consisting of two redistribution layers separated by insulating material and connected through insulator vias.

Key Features and Innovation

• Package structure with two redistribution layers.
• Insulating encapsulant for protecting the semiconductor die and vias.
• Through insulator vias connecting the layers.
• Dielectric layer with connecting portions for electrical connections.
• Semiconductor die placed on the dielectric layer.

Potential Applications

This technology can be used in various semiconductor devices, such as microprocessors, memory chips, and sensors.

Problems Solved

• Protects the semiconductor die and vias from external elements.
• Provides a reliable electrical connection between layers.
• Enhances the overall performance and durability of the semiconductor device.

Benefits

• Improved reliability and durability of semiconductor devices.
• Enhanced electrical connectivity between layers.
• Protection against external factors such as moisture and dust.

Commercial Applications

This technology can be applied in the manufacturing of advanced electronic devices, leading to more reliable and durable products in the market.

Prior Art

Readers can explore prior patents related to semiconductor packaging and interconnection technologies to understand the evolution of similar concepts.

Frequently Updated Research

Researchers are constantly working on improving semiconductor packaging techniques to enhance the performance and reliability of electronic devices.

Questions about Semiconductor Package Structure

What are the key components of the package structure described in the patent application?

The key components include two redistribution layers, insulating encapsulant, through insulator vias, dielectric layer, connecting portions, and a semiconductor die.

How does the insulating encapsulant contribute to the protection of the semiconductor device?

The insulating encapsulant shields the semiconductor die and vias from external factors like moisture and dust, ensuring the longevity and reliability of the device.

Original Abstract Submitted

A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.