18658589. ESD PROTECTION CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
ESD PROTECTION CIRCUIT
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Wun-Jie Lin of Hsinchu City (TW)
Kuo-Ji Chen of New Taipei City (TW)
ESD PROTECTION CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18658589 titled 'ESD PROTECTION CIRCUIT
The abstract describes an ESD clamp circuit with an ESD detection circuit connected between two terminals, featuring a discharge circuit with p-type and n-type transistors to establish ESD discharge paths.
- ESD clamp circuit with ESD detection circuit
- Discharge circuit with p-type and n-type transistors
- Establishment of ESD discharge paths
- Inclusion of a parasitic silicon controlled rectifier (SCR) in the second ESD discharge path
- Response to ESD events with control signals
- Connection of transistors to output nodes for discharge path control
Potential Applications: - Electronic devices - Integrated circuits - Circuit protection systems
Problems Solved: - Protection against ESD events - Prevention of damage to electronic components - Ensuring reliability of electronic systems
Benefits: - Enhanced ESD protection - Improved reliability of electronic devices - Cost-effective solution for ESD mitigation
Commercial Applications: Title: "ESD Clamp Circuit for Enhanced Circuit Protection" This technology can be utilized in various industries such as consumer electronics, automotive, telecommunications, and industrial automation for safeguarding electronic components against ESD damage.
Questions about ESD Clamp Circuit Technology: 1. How does the ESD detection circuit respond to ESD events?
- The ESD detection circuit outputs control signals in response to ESD events to trigger the discharge circuit.
2. What are the main advantages of using a discharge circuit with p-type and n-type transistors?
- The p-type and n-type transistors help establish effective ESD discharge paths for protecting electronic components.
Original Abstract Submitted
An ESD clamp circuit has an ESD detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. The ESD detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an ESD event. A discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. An n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. The drain is connected to the drain of the p-type transistor. The discharge circuit is configured to establish a first ESD discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second ESD discharge path in parallel with the first ESD discharge path. The second ESD discharge path includes a parasitic silicon controlled rectifier (SCR).
