18645551. INTEGRATED CIRCUIT DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
INTEGRATED CIRCUIT DEVICES
Organization Name
Inventor(s)
Junyoung Park of Hwaseong-si (KR)
Seunghun Lee of Hwaseong-si (KR)
INTEGRATED CIRCUIT DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18645551 titled 'INTEGRATED CIRCUIT DEVICES
The abstract describes an integrated circuit device with a semiconductor on insulator (SOI) substrate layer, fin-type active areas, nanosheet stacked structures, source/drain regions, and more.
- SOI substrate layer with base, insulating, and cover substrate layers
- Semiconductor substrate layer
- First and second fin-type active areas defined by trenches
- Nanosheet stacked structures parallel to each other above the active areas
- First and second source/drain regions extending into respective substrate layers
Potential Applications: - Advanced semiconductor devices - High-performance integrated circuits - Next-generation electronics
Problems Solved: - Enhancing device performance - Improving efficiency and speed of circuits
Benefits: - Increased functionality - Higher processing speeds - Reduced power consumption
Commercial Applications: Title: Advanced Semiconductor Devices for High-Performance Electronics This technology can be used in: - Consumer electronics - Telecommunications - Automotive industry
Questions about the technology: 1. How does the nanosheet stacked structure improve the performance of the integrated circuit device? 2. What are the advantages of having source/drain regions extending into different substrate layers?
Frequently Updated Research: - Ongoing studies on optimizing nanosheet structures for even better performance in integrated circuits.
Original Abstract Submitted
An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.
