18641986. MULTILAYER CERAMIC CAPACITOR simplified abstract (Murata Manufacturing Co., Ltd.)

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MULTILAYER CERAMIC CAPACITOR

Organization Name

Murata Manufacturing Co., Ltd.

Inventor(s)

Taro Sakai of Nagaokakyo-shi (JP)

MULTILAYER CERAMIC CAPACITOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 18641986 titled 'MULTILAYER CERAMIC CAPACITOR

The abstract of the patent application describes a multilayer ceramic capacitor with a unique structure involving internal electrode layers and a dielectric ceramic layer.

  • The capacitor includes a central layer portion with internal electrode layers and a dielectric ceramic layer, a peripheral layer portion, and a side margin.
  • The boundary between the peripheral layer portion and the side margin is curved from an imaginary line passing through the end of the internal electrode layer.
  • This design enhances the performance and efficiency of the capacitor.

Potential Applications: - Electronic devices - Power supplies - Circuit boards

Problems Solved: - Improved capacitor performance - Enhanced efficiency in electronic devices

Benefits: - Higher capacitance - Better electrical performance - Increased reliability

Commercial Applications: Title: Advanced Multilayer Ceramic Capacitors for Electronic Devices This technology can be used in various electronic devices, power supplies, and circuit boards, improving their performance and efficiency.

Questions about Multilayer Ceramic Capacitors: 1. How does the unique structure of this capacitor improve its performance? 

  - The unique structure enhances capacitance and electrical performance.

2. What are the potential applications of this technology in the electronics industry? 

  - This technology can be used in electronic devices, power supplies, and circuit boards for improved efficiency and reliability.


Original Abstract Submitted

A multilayer ceramic capacitor includes a laminate and an external electrode. The laminate includes a central layer portion in which first and second internal electrode layers are alternately laminated with a dielectric ceramic layer therebetween, a peripheral layer portion sandwiching the central layer portion in the lamination direction, and a side margin sandwiching the central layer portion and the peripheral layer portion in the width direction. When a point P indicates an end in the width direction of the internal electrode layer closest to a main surface of the laminate, and a point Q indicates a point where a boundary between the peripheral layer portion including the point P and the side margin including the point P intersects the main surface, and an imaginary line IL is drawn to pass through the point P and the point Q, the boundary is curved from the imaginary line IL.

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