18628804. INTERPOSER WITH WARPAGE-RELIEF TRENCHES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

INTERPOSER WITH WARPAGE-RELIEF TRENCHES

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Tsung-Yang Hsieh of Taipei City (TW)

Chien-Chang Lee of Miaoli County (TW)

Chia-Ping Lai of Hsinchu (TW)

Wen-Chung Lu of Hsinchu (TW)

Cheng-Kang Huang of Hsinchu (TW)

Mei-Shih Kuo of Hsinchu (TW)

Chih-Ai Huang of Hsinchu (TW)

INTERPOSER WITH WARPAGE-RELIEF TRENCHES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18628804 titled 'INTERPOSER WITH WARPAGE-RELIEF TRENCHES

The abstract describes a method for forming an integrated circuit (IC) chip package structure using an interposer with warpage-reducing trenches and warpage-relief material.

• Interposer provided with front and back surfaces, routing regions, and non-routing regions.
• Warpage-reducing trenches formed in non-routing regions to reduce warpage.
• Warpage-relief material deposited in trenches to further reduce warpage.
• IC dies bonded to the front surface of the interposer for packaging.

Potential Applications: - Semiconductor industry for IC chip packaging. - Electronics manufacturing for improved chip reliability.

Problems Solved: - Reducing warpage in IC chip packages. - Enhancing reliability of integrated circuits.

Benefits: - Improved chip performance and reliability. - Enhanced structural integrity of IC chip packages.

Commercial Applications: - Semiconductor companies for advanced IC packaging. - Electronics manufacturers for high-performance devices.

Questions about the technology: 1. How does the warpage-reducing trench help in reducing warpage in IC chip packages? 2. What are the advantages of using warpage-relief material in the trenches?

Frequently Updated Research: - Ongoing research on advanced packaging techniques in the semiconductor industry.

Original Abstract Submitted

A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.