18628127. Usage-Based Disturbance Counter Clearance simplified abstract (Micron Technology, Inc.)
Contents
Usage-Based Disturbance Counter Clearance
Organization Name
Inventor(s)
Mark Kalei Hadrick of Boise ID (US)
KeunSoo Song of Meridian ID (US)
John Christopher Sancon of Boise ID (US)
Kang-Yong Kim of Boise ID (US)
Usage-Based Disturbance Counter Clearance - A simplified explanation of the abstract
This abstract first appeared for US patent application 18628127 titled 'Usage-Based Disturbance Counter Clearance
Simplified Explanation: The patent application describes apparatuses and techniques for implementing usage-based disturbance counter clearance in memory devices. This involves clearing disturbance counters associated with memory rows to reduce the frequency of disturbance mitigation procedures.
Key Features and Innovation:
- Memory device with multiple rows and usage-based disturbance counters
- Logic that performs refresh operations on rows and clears disturbance counters
- Disturbance counters store the quantity of accesses to memory rows
- Reduces the need for disturbance mitigation procedures, saving power and avoiding denial-of-service periods
Potential Applications: This technology can be applied in various memory devices, such as DRAM and SRAM, to improve performance and efficiency by managing disturbance counters effectively.
Problems Solved:
- Reducing power consumption in memory devices
- Preventing denial-of-service periods in memory arrays
- Optimizing disturbance mitigation procedures for better performance
Benefits:
- Improved power efficiency in memory devices
- Enhanced reliability and longevity of memory arrays
- Optimal performance without disruption from disturbance events
Commercial Applications: Potential commercial applications include the integration of this technology in mobile devices, servers, and other computing systems to enhance memory performance and reduce power consumption.
Questions about Usage-Based Disturbance Counter Clearance: 1. How does clearing disturbance counters help in reducing power consumption in memory devices? 2. What are the potential long-term benefits of implementing usage-based disturbance counter clearance in memory arrays?
Frequently Updated Research: Stay updated on the latest advancements in memory device technology, particularly in the field of disturbance counter management and power optimization.
Original Abstract Submitted
Apparatuses and techniques for implementing usage-based disturbance counter clearance are described. In example implementations, a memory device includes a memory array having multiple rows. The memory device also includes multiple usage-based disturbance counters that are associated with the memory array. The memory device further includes logic that performs a refresh operation on a row of the multiple rows responsive to a refresh command. The logic also clears a usage-based disturbance counter of the multiple usage-based disturbance counters responsive to the refresh command. Here, the usage-based disturbance counter stores a quantity of accesses to the row of the multiple rows. This can reduce a frequency of performing usage-based disturbance mitigation procedures that would otherwise be applied to the multiple usage-based disturbance counters, thereby saving power and avoiding denial-of-service periods with the memory array.
