18622486. COPPERLESS REGIONS TO CONTROL PLATING GROWTH simplified abstract (Intel Corporation)

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COPPERLESS REGIONS TO CONTROL PLATING GROWTH

Organization Name

Intel Corporation

Inventor(s)

Brandon C. Marin of Gilbert AZ (US)

Jung Kyu Han of Chandler AZ (US)

Thomas Heaton of Mesa AZ (US)

Ali Lehaf of Phoenix AZ (US)

Rahul Manepalli of Chandler AZ (US)

Srinivas Pietambaram of Chandler AZ (US)

Jacob Vehonsky of Gilbert AZ (US)

COPPERLESS REGIONS TO CONTROL PLATING GROWTH - A simplified explanation of the abstract

This abstract first appeared for US patent application 18622486 titled 'COPPERLESS REGIONS TO CONTROL PLATING GROWTH

The patent application relates to manufacturing a package with a substrate, a copper layer, and bumps on one side of the substrate.

  • The substrate has a first side with a copper layer and bumps, and a second side without a copper layer.
  • The layout of regions on the first side varies the growth of bumps during a plating process by modifying local copper density.
  • This innovation allows for precise control over the plating process, resulting in more uniform bump formation.

Potential Applications:

  • Semiconductor packaging
  • Electronics manufacturing
  • Microchip production

Problems Solved:

  • Ensuring uniform bump formation on the substrate
  • Controlling the plating process for optimal results

Benefits:

  • Improved quality and consistency in package manufacturing
  • Enhanced performance of electronic components
  • Cost-effective production process

Commercial Applications:

  • Semiconductor industry
  • Electronics manufacturing companies
  • Research and development in microchip technology

Questions about the technology: 1. How does the variation in copper density affect the growth of bumps during the plating process? 2. What are the advantages of having regions on the substrate with different copper densities?

Frequently Updated Research: New developments in plating processes for semiconductor packaging Advancements in bump formation techniques for electronic components.


Original Abstract Submitted

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.