18612239. NONVOLATILE SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Takashi Maeda of Yokohama (JP)
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18612239 titled 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation: The patent application describes a method for selectively erasing sub-blocks in a memory device by applying different voltages to various lines within the memory block.
Key Features and Innovation:
- Selective erasing of sub-blocks in a memory device.
- Application of different voltages to bit lines, word lines, select gate lines, and source lines for erasing operations.
- Ability to perform erase operations in specific sub-blocks while leaving others unaffected.
Potential Applications: This technology can be used in various memory devices such as flash memory, solid-state drives, and other non-volatile memory systems where selective erasing of data is required.
Problems Solved:
- Efficient and targeted erasing of specific sub-blocks in a memory device.
- Minimization of data loss by selectively erasing only the necessary information.
Benefits:
- Improved data management in memory devices.
- Enhanced reliability and longevity of memory systems.
- Increased efficiency in erasing operations.
Commercial Applications: This technology can be utilized in the development of advanced memory devices for consumer electronics, data storage systems, and industrial applications, enhancing data security and performance.
Prior Art: Readers can explore prior patents related to memory device erasing techniques, voltage application methods, and selective data deletion in memory systems to gain a deeper understanding of the existing technology landscape.
Frequently Updated Research: Researchers may find updated studies on memory device optimization, data management techniques, and advancements in non-volatile memory technologies relevant to this patent application.
Questions about Memory Device Erasing: 1. How does the selective erasing process in memory devices differ from traditional full erasing methods? 2. What are the potential implications of using different voltages for erasing operations in memory systems?
Original Abstract Submitted
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the 10 selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
