18608460. REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE simplified abstract (MICRON TECHNOLOGY, INC.)
Contents
REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE
Organization Name
Inventor(s)
Scott E. Schaefer of Boise ID (US)
Aaron P. Boehm of Boise ID (US)
REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18608460 titled 'REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE
The abstract describes methods, systems, and devices for redundancy-based error detection in a memory device.
- Memory device reads multiple copies of a codeword from memory.
- Generates an error detection bit for each codeword copy to indicate error detection.
- Compares codeword copies and generates match bits to indicate if corresponding portions match.
- Determines error status of each codeword using error detection bits and match bits.
Potential Applications: - Data storage systems - Communication systems - Error correction in computing devices
Problems Solved: - Error detection in memory devices - Ensuring data integrity - Improving reliability of memory systems
Benefits: - Enhanced error detection capabilities - Increased data reliability - Improved performance of memory devices
Commercial Applications: Title: "Enhancing Data Integrity in Memory Devices" This technology can be used in various industries such as data centers, telecommunications, and consumer electronics to improve data reliability and performance of memory systems.
Questions about Redundancy-Based Error Detection in Memory Devices: 1. How does redundancy-based error detection improve data reliability in memory devices?
- Redundancy-based error detection allows memory devices to detect and correct errors, ensuring data integrity and reliability.
2. What are the potential applications of this technology beyond memory devices?
- This technology can be applied in various systems where error detection and correction are critical, such as communication networks and data storage systems.
Original Abstract Submitted
Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.
