18607849. CHIP-ON-FILM PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
CHIP-ON-FILM PACKAGE
Organization Name
Inventor(s)
CHIP-ON-FILM PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18607849 titled 'CHIP-ON-FILM PACKAGE
The abstract describes a chip-on-film (COF) package with various intricate patterns and layers for electrical connections.
- Base film with upper patterns on one surface and lower patterns on the other surface
- Upper insulating layer covering some upper patterns
- Inner via plugs connecting upper patterns to lower patterns through the base film
- Specific electrical connections between inner patterns and via plugs
Potential Applications: - Semiconductor packaging - Electronics manufacturing - Display technologies
Problems Solved: - Efficient electrical connections in a compact package - Improved signal transmission in electronic devices
Benefits: - Enhanced performance in electronic devices - Space-saving design for compact devices
Commercial Applications: Title: Advanced COF Packaging for Electronics Industry This technology can be used in various electronic devices like smartphones, tablets, and displays, improving their performance and reliability.
Questions about COF Packaging: 1. How does this technology improve the efficiency of electrical connections in electronic devices?
- This technology enables precise and reliable electrical connections between different components, enhancing the overall performance of electronic devices.
2. What are the potential challenges in implementing COF packaging in mass production?
- Mass production of COF packages may require specialized equipment and processes to ensure consistent quality and reliability.
Original Abstract Submitted
A chip-on-film (COF) package including a base film having facing first and second surfaces; a first upper pattern on the first surface and extending in a first direction; second upper patterns on the first surface, the second upper patterns including inner patterns and outer patterns that are spaced apart from each other in the first direction; an upper insulating layer covering the first upper pattern and part of the second upper patterns; lower patterns on the second surface and electrically connecting the inner patterns to the outer patterns; and inner via plugs passing through the base film and electrically connecting the inner patterns of the second upper patterns to the lower patterns, wherein at least one inner pattern is electrically connected to the inner via plug in a region that is not covered by the upper insulating layer.
