18606876. CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS simplified abstract (Intel Corporation)
Contents
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
Organization Name
Inventor(s)
Srinivas Pietambaram of Chandler AZ (US)
Deepak Kulkarni of Chandler AZ (US)
Rahul Manepalli of Chandler AZ (US)
Xiaoying Guo of Chandler AZ (US)
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18606876 titled 'CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
The abstract of this patent application describes electronic packages and methods of forming them. The electronic package includes a mold layer with embedded dies, where each die's surface is coplanar with the mold layer. Additionally, a second die is embedded in the mold layer between the first dies and the second surface of the mold layer.
- Mold layer with embedded dies
- Coplanar surfaces of the dies with the mold layer
- Second die embedded in the mold layer
Potential Applications: - Electronic packaging industry - Semiconductor manufacturing
Problems Solved: - Efficient and compact electronic packaging - Improved die embedding process
Benefits: - Enhanced performance due to compact design - Simplified manufacturing process
Commercial Applications: Title: Advanced Electronic Packaging Technology for Semiconductor Industry This technology can be used in the semiconductor industry for compact and efficient electronic packaging, leading to improved performance and simplified manufacturing processes. The market implications include increased demand for advanced electronic packaging solutions in various electronic devices.
Prior Art: Readers can start their search for prior art related to this technology by looking into patents and research papers on die embedding processes in electronic packaging.
Frequently Updated Research: Researchers are constantly exploring new materials and techniques for die embedding in electronic packages to further improve performance and efficiency.
Questions about Electronic Packaging Technology: 1. What are the key advantages of embedding dies in a mold layer in electronic packaging? 2. How does the coplanar surface design of the dies with the mold layer contribute to the overall performance of the electronic package?
Original Abstract Submitted
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
