18604691. PACKAGE COMPONENT WITH STEPPED PASSIVATION LAYER simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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PACKAGE COMPONENT WITH STEPPED PASSIVATION LAYER

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Ming-Da Cheng of Taoyuan City (TW)

Tzy-Kuang Lee of Taichung (TW)

Song-Bor Lee of Zhubei City (TW)

Wen-Hsiung Lu of Tainan City (TW)

Po-Hao Tsai of Taoyuan City (TW)

Wen-Che Chang of Taichung (TW)

PACKAGE COMPONENT WITH STEPPED PASSIVATION LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 18604691 titled 'PACKAGE COMPONENT WITH STEPPED PASSIVATION LAYER

The method described in the abstract involves the formation of a first conductive feature, deposition of a passivation layer on the sidewall and top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to create a step.

  • A first conductive feature is formed.
  • A passivation layer is deposited on the sidewall and top surface of the first conductive feature.
  • The passivation layer is etched to expose the first conductive feature.
  • A step is created by recessing a first top surface of the passivation layer.
  • A planarization layer is formed on the passivation layer.
  • A second conductive feature is formed to make contact with the first conductive feature.

Potential Applications: - Semiconductor manufacturing - Microelectronics industry - Integrated circuit fabrication

Problems Solved: - Improving contact between conductive features - Enhancing the reliability of electronic devices - Increasing efficiency in semiconductor processes

Benefits: - Enhanced electrical connectivity - Improved device performance - Increased yield in manufacturing processes

Commercial Applications: Title: Advanced Semiconductor Manufacturing Process for Enhanced Device Performance This technology can be utilized in the production of various electronic devices, such as smartphones, computers, and automotive electronics, to improve their overall performance and reliability.

Questions about the technology: 1. How does the method described in the patent application improve the contact between conductive features? 2. What are the potential implications of using this technology in the semiconductor industry?


Original Abstract Submitted

A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

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