18604613. SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Chin-Hua Wang of New Taipei City (TW)
Shu-Shen Yeh of Taoyuan City (TW)
Po-Chen Lai of Hsinchu County (TW)
Po-Yao Lin of Zhudong Township (TW)
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK - A simplified explanation of the abstract
This abstract first appeared for US patent application 18604613 titled 'SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK
The semiconductor structure described in the patent application includes a substrate with conductive pads and conductive bumps on the pads, as well as a multi-tiered solder-resist structure.
- The multi-tiered solder-resist structure consists of a first tier and a second tier, each with dielectric material and conductive bump openings.
- The first tier has a certain width measured between its inner sidewalls, while the second tier overlies the first tier and has a different width measured between its inner sidewalls.
- The ratio of the width of the first tier to the width of the second tier falls within a specific range from 1.1:1 to 2:1.
Potential Applications: - This technology could be used in the manufacturing of semiconductor devices to improve the reliability and performance of the devices. - It may find applications in various electronic products where precise and reliable connections are crucial.
Problems Solved: - Provides a more robust and reliable structure for semiconductor devices. - Helps in ensuring proper connections between different components of electronic devices.
Benefits: - Enhanced reliability and performance of semiconductor devices. - Improved manufacturing processes for electronic products.
Commercial Applications: - This technology could be utilized in the production of smartphones, tablets, computers, and other electronic devices to enhance their overall quality and durability.
Questions about the technology: 1. How does the ratio of widths between the first and second tiers impact the performance of the semiconductor structure? 2. What are the specific advantages of using a multi-tiered solder-resist structure in semiconductor devices?
Original Abstract Submitted
Some embodiments relate to a semiconductor structure including a substrate with conductive pads and conductive bumps disposed on the conductive pads, respectively. A multi-tiered solder-resist structure includes a first tier and a second tier. The first tier includes a first dielectric material and first conductive bump openings defined by inner sidewalls of the first tier. The first tier has a first width measured through the first dielectric material between the inner sidewalls of the first tier in a cross-sectional view. The second tier overlies the first tier and includes a second dielectric material and second conductive bump openings defined by inner sidewalls of the second tier. The second tier has a second width measured through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view. A ratio of the first width to the second width ranges from 1.1:1 to 2:1.
