18601774. PACKAGE STACKING USING CHIP TO WAFER BONDING simplified abstract (Intel Corporation)

PACKAGE STACKING USING CHIP TO WAFER BONDING

Organization Name

Intel Corporation

Inventor(s)

Georg Seidemann of Landshut (DE)

Klaus Reingruber of Langquaid (DE)

Christian Geissler of Teugn (DE)

Sven Albers of Regensburg (DE)

Andreas Wolter of Regensburg (DE)

Marc Dittes of Regensburg (DE)

Richard Patten of Langquaid (DE)

PACKAGE STACKING USING CHIP TO WAFER BONDING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18601774 titled 'PACKAGE STACKING USING CHIP TO WAFER BONDING

Simplified Explanation: The patent application is about package stacking using chip to wafer bonding, where semiconductor dies and components are stacked with dielectric layers in between.

Key Features and Innovation:

• Package stacking using chip to wafer bonding
• Stacked layers of semiconductor dies and components
• Dielectric layers between stacked layers
• Thinning of stacked layers to specific thicknesses

Potential Applications: This technology can be used in the semiconductor industry for advanced packaging solutions, such as in microprocessors, memory devices, and sensors.

Problems Solved: This technology addresses the need for compact and efficient packaging of semiconductor dies and components in electronic devices.

Benefits:

• Improved performance and reliability of electronic devices
• Enhanced thermal management
• Reduction in overall size of electronic products

Commercial Applications: The technology can be applied in the manufacturing of smartphones, tablets, laptops, and other consumer electronics, as well as in industrial and automotive applications.

Prior Art: Readers can explore prior art related to chip to wafer bonding, semiconductor packaging, and advanced packaging techniques in the semiconductor industry.

Frequently Updated Research: Researchers are constantly exploring new materials and processes to further enhance the efficiency and performance of package stacking using chip to wafer bonding.

Questions about Package Stacking Using Chip to Wafer Bonding: 1. What are the key advantages of using chip to wafer bonding in semiconductor packaging? 2. How does package stacking using chip to wafer bonding compare to other advanced packaging techniques in terms of performance and cost-effectiveness?

Original Abstract Submitted

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.