18600957. MULTI-LEVEL MEMRISTOR ELEMENTS simplified abstract (Cirrus Logic International Semiconductor Ltd.)
Contents
MULTI-LEVEL MEMRISTOR ELEMENTS
Organization Name
Cirrus Logic International Semiconductor Ltd.
Inventor(s)
John P. Lesso of Edinburgh (GB)
James T. Deas of Edinburgh (GB)
MULTI-LEVEL MEMRISTOR ELEMENTS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18600957 titled 'MULTI-LEVEL MEMRISTOR ELEMENTS
Simplified Explanation: The patent application describes a two-terminal multi-level memristor element created from binary memristors, capable of adjusting resistance based on unary or binary code words. It also details the implementation of a circuit, like a synapse circuit, using this multi-level memristor element.
- The invention involves a two-terminal multi-level memristor element synthesized from binary memristors.
- This memristor element can vary its resistance based on unary or binary code words.
- The technology allows for the creation of circuits, such as synapse circuits, utilizing the multi-level memristor element.
Potential Applications: The technology can be applied in neuromorphic computing, artificial intelligence, and advanced memory systems.
Problems Solved: The innovation addresses the need for efficient and adaptable resistance elements in circuit design.
Benefits: The technology offers flexibility in resistance adjustment, enabling versatile circuit configurations and applications.
Commercial Applications: "Multi-level Memristor Element for Advanced Circuit Design" can revolutionize the fields of neuromorphic computing, artificial intelligence, and memory systems, potentially leading to more efficient and powerful electronic devices.
Questions about Multi-level Memristor Element: 1. How does the multi-level memristor element differ from traditional resistors in circuit design? 2. What are the potential implications of using multi-level memristor elements in artificial intelligence systems?
Frequently Updated Research: Researchers are continuously exploring the optimization of multi-level memristor elements for enhanced performance in various applications.
Original Abstract Submitted
There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
