18598585. Memory Circuitry And Methods Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)
Contents
Memory Circuitry And Methods Used In Forming Memory Circuitry
Organization Name
Inventor(s)
Kamal M. Karda of Boise ID (US)
David Daycock of Boise ID (US)
Memory Circuitry And Methods Used In Forming Memory Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 18598585 titled 'Memory Circuitry And Methods Used In Forming Memory Circuitry
The memory circuitry described in the patent application consists of vertically-alternating tiers of insulative material and memory cells, each comprising a transistor with a first source/drain region, a second source/drain region, and a channel region between them, along with a gate proximate to the channel region and a capacitor with a first and second electrode and a capacitor insulator.
- The first capacitor electrode is directly connected to the first source/drain region, while the second capacitor electrode of multiple capacitors is connected to each other.
- Digitlines run vertically through the tiers, with the second source/drain regions of transistors in different memory-cell tiers directly connected to individual digitlines.
- Wordlines in each memory-cell tier include the gates of multiple transistors, with lower tiers having wider wordlines than higher tiers directly above them.
Potential Applications: - This memory circuitry could be used in various electronic devices such as smartphones, computers, and servers to enhance memory storage and performance. - It could also find applications in data centers for efficient data processing and storage.
Problems Solved: - The memory circuitry addresses the need for improved memory storage and access speeds in electronic devices. - It provides a more compact and efficient way to organize memory cells in vertical tiers.
Benefits: - Increased memory capacity and faster data access speeds. - Enhanced overall performance of electronic devices. - More efficient use of space in memory storage systems.
Commercial Applications: Title: Advanced Memory Circuitry for Enhanced Data Storage This technology could be commercially applied in the development of next-generation electronic devices, data centers, and other computing systems to improve memory capabilities and overall performance.
Questions about Memory Circuitry: 1. How does the vertical tier structure of the memory circuitry improve memory performance? The vertical tier structure allows for more memory cells to be packed in a smaller space, increasing storage capacity and access speeds.
2. What are the potential challenges in implementing this advanced memory circuitry in commercial electronic devices? Implementing this technology in commercial devices may require redesigning existing memory architectures and ensuring compatibility with different hardware configurations.
Original Abstract Submitted
Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A gate is operatively-proximate the channel region. A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The first capacitor electrode is directly electrically coupled to the first source/drain region. The second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. Digitlines extend elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines. A wordline is in individual of the memory-cell tiers that comprises the gate of multiple of the individual transistors in the individual memory-cell tiers. The wordline in a lower of the memory-cell tiers has a greater minimum width than a minimum width of the wordline in a higher of the memory-cell tiers that is directly above the lower memory-cell tier. Methods are also disclosed.
