18597215. HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE simplified abstract (Texas Instruments Incorporated)

From WikiPatents
Jump to navigation Jump to search

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

Organization Name

Texas Instruments Incorporated

Inventor(s)

Arnab Khawas of Bangalore (IN)

Badarish Subbannavar of Bangalore (IN)

Madhavan Sainath Rao Pissay of Hyderbad (IN)

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18597215 titled 'HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

The abstract describes a patent application for a scan flip-flop circuit, which includes multiple transistors and an input multiplexer.

  • The scan flip-flop includes a first transistor and a second transistor connected to a data input.
  • It also includes a third transistor connected to a clock input and a fourth transistor connected to an inverse clock input.
  • A fifth transistor is coupled to a scan enable input and the first transistor, while a sixth transistor is coupled to an inverse scan enable input and the second transistor.
  • An input multiplexer is part of the scan flip-flop, consisting of a seventh transistor and eighth transistor connected to the scan data input, a ninth transistor connected to the scan enable input, and a tenth transistor connected to the inverse scan enable input.
  • The input multiplexer includes diode-connected transistors between voltage rails and the respective transistors for signal routing.

Potential Applications: - Integrated circuits - Digital electronics - Semiconductor technology

Problems Solved: - Efficient data storage and retrieval - Improved signal routing - Enhanced circuit performance

Benefits: - Faster data processing - Reduced power consumption - Higher reliability

Commercial Applications: Title: "Advanced Scan Flip-Flop Technology for Integrated Circuits" This technology can be used in microprocessors, memory chips, and other digital devices to improve data handling and processing speed.

Questions about Scan Flip-Flop Technology: 1. How does the input multiplexer enhance the functionality of the scan flip-flop circuit? The input multiplexer allows for flexible routing of signals based on the scan enable input, improving data handling efficiency.

2. What advantages does using multiple transistors in the scan flip-flop circuit offer over traditional flip-flop designs? Using multiple transistors allows for more precise control over data input and clock signals, leading to improved performance and reliability.


Original Abstract Submitted

In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.

Retrieved from "http://wikipatents.org/index.php?title=18597215._HOLD_TIME_IMPROVED_LOW_AREA_FLIP-FLOP_ARCHITECTURE_simplified_abstract_(Texas_Instruments_Incorporated)&oldid=80898"