18596240. THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
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THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18596240 titled 'THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE
The abstract describes a three-dimensional semiconductor package with multiple layers and chips interconnected within the package.
- Package substrate with first and second surfaces
- First redistribution layer on the first surface of the package substrate
- First chip on the first surface of the first redistribution layer
- First through silicon vias connecting the first chip to the first redistribution layer
- First connection terminals connected to one ends of the first through silicon vias
- Second redistribution layer on the second surface of the package substrate
- Second chip on the second surface of the second redistribution layer
Potential Applications: - Advanced electronic devices - Semiconductor industry - Integrated circuits
Problems Solved: - Improved connectivity within semiconductor packages - Enhanced performance of electronic devices
Benefits: - Higher efficiency in data transfer - Increased reliability of semiconductor packages - Compact design for space-saving applications
Commercial Applications: - Consumer electronics - Telecommunications - Automotive industry
Questions about the technology: 1. How does the three-dimensional design of the semiconductor package improve performance? 2. What are the advantages of using through silicon vias in semiconductor packaging?
Frequently Updated Research: - Ongoing developments in three-dimensional packaging technology - Research on optimizing signal transmission within semiconductor packages
Original Abstract Submitted
A three-dimensional semiconductor package including: a package substrate having a first surface and a second surface opposite to the first surface; a first redistribution layer on the first surface of the package substrate, the first redistribution layer having a first surface and a second surface opposite to each other; a first chip on the first surface of the first redistribution layer, electrically connected to the first redistribution layer, and including first through silicon vias; first connection terminals electrically connected to one ends of the first through silicon vias; a second redistribution layer on the second surface of the package substrate, the second redistribution layer having a first surface and a second surface opposite to each other, the first surface of the second redistribution layer facing the second surface of the package substrate; and a second chip on the second surface of the second redistribution layer.
