18591580. SEMICONDUCTOR MODULE ARRANGEMENT simplified abstract (Infineon Technologies AG)
Contents
SEMICONDUCTOR MODULE ARRANGEMENT
Organization Name
Inventor(s)
Christoph Bayer of Eussenheim (DE)
[[:Category:Matthias B�rger of Bad Wünnenberg (DE)|Matthias B�rger of Bad Wünnenberg (DE)]][[Category:Matthias B�rger of Bad Wünnenberg (DE)]]
SEMICONDUCTOR MODULE ARRANGEMENT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18591580 titled 'SEMICONDUCTOR MODULE ARRANGEMENT
The patent application describes a power semiconductor module arrangement that includes a structured first metallization layer with multiple sub-sections, each covered by an electrically conducting element to increase the cross-sectional area.
- The arrangement consists of a substrate with a dielectric insulation layer and a first metallization layer on one surface.
- At least one semiconductor body is attached to the first metallization layer via an electrically conductive connection layer.
- Electrically conducting elements are placed on the first metallization layer, each covering a subarea of a sub-section to enhance conductivity.
- The first metallization layer has a uniform thickness in a vertical direction, perpendicular to the dielectric insulation layer's surface.
- Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body.
Potential Applications: - Power electronics - Renewable energy systems - Electric vehicles
Problems Solved: - Improved conductivity and heat dissipation in power semiconductor modules - Enhanced performance and reliability of electronic devices
Benefits: - Increased efficiency and power handling capacity - Reduced heat generation and improved thermal management - Extended lifespan of power semiconductor modules
Commercial Applications: Title: Enhanced Power Semiconductor Modules for High-Performance Electronics This technology can be utilized in various industries such as automotive, renewable energy, industrial automation, and consumer electronics for high-power applications.
Questions about the technology: 1. How does the structured first metallization layer improve the performance of power semiconductor modules? 2. What are the potential cost-saving benefits of using this innovative arrangement in electronic devices?
Original Abstract Submitted
A power semiconductor module arrangement includes: a substrate having a dielectric insulation layer and a first metallization layer arranged on a first surface of the dielectric insulation layer; at least one semiconductor body arranged on and attached to the first metallization layer by an electrically conductive connection layer; and at least one electrically conducting element arranged on the first metallization layer. The first metallization layer is a structured layer having a plurality of different sub-sections. The first metallization layer has a uniform thickness in a vertical direction, the vertical direction being perpendicular to the first surface of the dielectric insulation layer. Each electrically conducting element is arranged on and covers a subarea of a sub-section, thereby increasing a cross-sectional area of the subarea of the respective sub-section. Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body arranged thereon.
