18588699. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Minjun Bae of Hwaseong-si (KR)
Gwangjae Jeon of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18588699 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
The semiconductor package described in the patent application includes a redistribution substrate, a semiconductor chip on the top surface of the redistribution substrate, and a solder terminal on the bottom surface of the redistribution substrate.
Key Features and Innovation:
- The redistribution substrate features an under-bump pattern in contact with the solder terminal, a dielectric layer on the sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern.
- The under-bump pattern has central and edge regions, with the edge region having a higher top surface level than the central region.
- The angle between the bottom surface and the sidewall of the under-bump pattern falls within a range of 110° to 140°.
Potential Applications: This technology can be applied in the manufacturing of advanced semiconductor packages for various electronic devices.
Problems Solved: This innovation addresses the need for improved semiconductor packaging solutions with enhanced performance and reliability.
Benefits:
- Enhanced performance and reliability of semiconductor packages.
- Improved thermal management capabilities.
- Increased efficiency in electronic device manufacturing processes.
Commercial Applications: This technology can be utilized in the production of high-performance electronic devices such as smartphones, tablets, and computers, enhancing their overall functionality and durability.
Questions about Semiconductor Packages: 1. How does the angle between the bottom surface and the sidewall of the under-bump pattern impact the performance of the semiconductor package? 2. What are the potential cost savings associated with implementing this innovative semiconductor packaging technology?
Frequently Updated Research: Researchers are continuously exploring new materials and manufacturing techniques to further enhance the performance and reliability of semiconductor packages. Stay updated on the latest advancements in this field for potential future applications.
Original Abstract Submitted
Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.
