18584282. SOURCE/DRAIN EPITAXIAL LAYER PROFILE simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
SOURCE/DRAIN EPITAXIAL LAYER PROFILE
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Hsin-Chi Chen of Tainan City (TW)
Kun-Tsang Chuang of Maoli (TW)
SOURCE/DRAIN EPITAXIAL LAYER PROFILE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18584282 titled 'SOURCE/DRAIN EPITAXIAL LAYER PROFILE
The present disclosure describes a method to reduce facet formation in source/drain silicon germanium (SiGe) epitaxial layers by utilizing an isolation region and doping with germanium (Ge) to form Ge-doped regions.
- Formation of an isolation region around a semiconductor layer and a gate structure.
- Deposition of first photoresist structures over the gate structure, isolation region, and semiconductor layer for doping with Ge.
- Disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions to create openings.
- Growing a SiGe epitaxial stack in the openings to mitigate facet formation.
Potential Applications: - Semiconductor manufacturing - Integrated circuit fabrication - Nanotechnology research
Problems Solved: - Facet formation in SiGe epitaxial layers - Improving semiconductor device performance
Benefits: - Enhanced semiconductor device reliability - Increased efficiency in integrated circuit production
Commercial Applications: Title: Advanced Semiconductor Manufacturing Method for Facet Mitigation This technology can be applied in the production of high-performance semiconductor devices, leading to improved functionality and reliability in various electronic applications.
Prior Art: Readers can explore prior research on SiGe epitaxial layer fabrication methods and semiconductor device manufacturing processes to gain a deeper understanding of the advancements in this field.
Frequently Updated Research: Researchers are continually exploring new techniques to enhance semiconductor device performance and optimize epitaxial layer growth processes. Stay updated on the latest developments in this area to leverage cutting-edge technologies for future applications.
Questions about SiGe Epitaxial Layer Facet Mitigation: 1. How does the method described in the patent application improve the quality of SiGe epitaxial layers? 2. What are the key advantages of using Ge doping in reducing facet formation in semiconductor devices?
Original Abstract Submitted
The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
