18583341. Packet Cache System and Method simplified abstract (Google LLC)

Packet Cache System and Method

Organization Name

Google LLC

Inventor(s)

Jiazhen Zheng of Santa Clara CA (US)

Srinivas Vaduvatha of San Jose CA (US)

Hugh McEvoy Walsh of Los Gatos CA (US)

Prashant R. Chandra of San Jose CA (US)

Abhishek Agarwal of Santa Clara CA (US)

Weihuang Wang of Los Gatos CA (US)

Weiwei Jiang of Santa Clara CA (US)

Packet Cache System and Method - A simplified explanation of the abstract

This abstract first appeared for US patent application 18583341 titled 'Packet Cache System and Method

The abstract describes a packet cache system that includes a cache memory allocator, a hash table, a cache memory, and an eviction engine. The cache memory allocator receives a memory address for a non-cache memory and associates it with a cache memory address. The hash table stores the memory address and cache memory address as key-value pairs. The cache memory stores packets at locations indicated by the cache memory address. The eviction engine determines which cached packets to remove from the cache memory and place in the non-cache memory when the cache memory is full.

• Cache memory allocator assigns memory addresses to packets and associates them with cache memory addresses
• Hash table stores memory addresses and cache memory addresses as key-value pairs
• Cache memory stores packets based on cache memory addresses
• Eviction engine manages removal of cached packets from cache memory to non-cache memory when cache memory is full

Potential Applications: - Network routers - Data centers - Internet of Things (IoT) devices

Problems Solved: - Efficient memory management in packet processing systems - Optimizing cache memory usage

Benefits: - Improved system performance - Reduced latency in packet processing

Commercial Applications: Title: "Enhancing Packet Processing Efficiency with Advanced Cache Memory System" This technology can be used in network infrastructure equipment, data centers, and IoT devices to optimize packet processing and improve overall system performance.

Prior Art: Researchers have explored various cache memory management techniques in packet processing systems, but this specific approach may offer unique advantages in terms of efficiency and scalability.

Frequently Updated Research: Ongoing research in cache memory optimization and packet processing efficiency may provide further insights into the potential enhancements of this technology.

Questions about Packet Cache System: 1. How does the cache memory allocator determine the cache memory address for a given memory address? 2. What criteria does the eviction engine use to select which cached packets to remove from the cache memory?

Original Abstract Submitted

A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.