18583294. MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME simplified abstract (SK hynix Inc.)
Contents
MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
HEEEUN Choi of Icheon-si Gyeonggi-do (KR)
Yeong Han Jeong of Icheon-si Gyeonggi-do (KR)
MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18583294 titled 'MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
The memory apparatus described in the patent application includes a circuit that decodes addresses and generates test redundancy addresses based on input from a memory controller. Another circuit checks whether the test redundancy address is replacing a failed address, allowing for ECC test operations using the test redundancy address.
- Address decoding circuit generates test redundancy addresses based on input from memory controller
- Redundancy address check circuit determines if test redundancy address replaces a failed address
- Enables ECC test operations using test redundancy address
Potential Applications: - Memory systems - Data storage devices - Error correction in electronic systems
Problems Solved: - Efficient replacement of failed memory addresses - Improved error correction capabilities
Benefits: - Enhanced reliability of memory systems - Increased data integrity - Simplified error correction processes
Commercial Applications: Title: "Advanced Memory Error Correction Technology for Enhanced Data Integrity" This technology can be utilized in: - Computer servers - Networking equipment - Consumer electronics
Questions about Memory Apparatus with Address Decoding and Redundancy Check Circuit: 1. How does the address decoding circuit generate test redundancy addresses? The address decoding circuit generates test redundancy addresses based on input from the memory controller, allowing for efficient error correction operations.
2. What is the role of the redundancy address check circuit in the memory apparatus? The redundancy address check circuit determines whether the test redundancy address is replacing a failed address, enabling ECC test operations to be performed effectively.
Original Abstract Submitted
A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.
