18582746. SELECTIVE DEPOSITION OF A PROTECTIVE LAYER TO REDUCE INTERCONNECT STRUCTURE CRITICAL DIMENSIONS simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

SELECTIVE DEPOSITION OF A PROTECTIVE LAYER TO REDUCE INTERCONNECT STRUCTURE CRITICAL DIMENSIONS

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Hsi-Wen Tien of Xinfeng Township (TW)

Chung-Ju Lee of Hsinchu City (TW)

Chih Wei Lu of Hsinchu City (TW)

Hsin-Chieh Yao of Hsinchu City (TW)

Yu-Teng Dai of New Taipei City (TW)

Wei-Hao Liao of Taichung City (TW)

SELECTIVE DEPOSITION OF A PROTECTIVE LAYER TO REDUCE INTERCONNECT STRUCTURE CRITICAL DIMENSIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18582746 titled 'SELECTIVE DEPOSITION OF A PROTECTIVE LAYER TO REDUCE INTERCONNECT STRUCTURE CRITICAL DIMENSIONS

Simplified Explanation

The patent application describes an integrated chip with protective layers surrounding interconnect vias and wires.

• The integrated chip has an interconnect dielectric layer over a substrate.
• An interconnect via and wire are within the dielectric layer.
• A protective layer surrounds the interconnect via, extending from its outer sidewall to the wire.
• The protective layer extends below the interconnect via in a first cross-sectional view.

Key Features and Innovation

• Integration of protective layers around interconnect vias and wires.
• Enhanced protection for interconnect components within the chip.

Potential Applications

This technology can be applied in various semiconductor devices, such as microprocessors, memory chips, and integrated circuits.

Problems Solved

• Protection of interconnect components from external factors.
• Ensuring the reliability and longevity of the integrated chip.

Benefits

• Improved durability and performance of semiconductor devices.
• Enhanced reliability in electronic systems.

Commercial Applications

• This technology can be utilized in the manufacturing of advanced electronic devices for consumer electronics, telecommunications, and automotive industries.

Prior Art

Readers can explore prior patents related to integrated chip design, interconnect technologies, and protective layers in semiconductor devices.

Frequently Updated Research

Stay updated on advancements in semiconductor manufacturing processes, materials science, and chip design for potential improvements in integrated chip technology.

Questions about Integrated Chip Technology

What are the key advantages of using protective layers in integrated chips?

Protective layers enhance the durability and reliability of interconnect components, ensuring the long-term performance of semiconductor devices.

How does the integration of protective layers impact the overall design and functionality of integrated chips?

By incorporating protective layers, integrated chips can withstand environmental stressors and maintain stable operation, contributing to the longevity of electronic systems.

Original Abstract Submitted

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.