18582433. SEMICONDUCTOR STORAGE DEVICE simplified abstract (Kioxia Corporation)
Contents
SEMICONDUCTOR STORAGE DEVICE
Organization Name
Inventor(s)
Masaharu Wada of Yokohama (JP)
Takayuki Miyazaki of Tokyo (JP)
Takashi Inukai of Yokohama (JP)
SEMICONDUCTOR STORAGE DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18582433 titled 'SEMICONDUCTOR STORAGE DEVICE
Simplified Explanation: The patent application describes a memory system with cell arrays for read and write operations, connected to selection lines and sense amplifiers. The logical row addresses differ between the first and second sub arrays.
Key Features and Innovation:
- Memory system with cell arrays for read and write operations
- Selection lines connected to logical row addresses
- Sense amplifiers for data detection
- Different logical row addresses in first and second sub arrays
Potential Applications: This technology can be used in various memory storage devices such as computer RAM, solid-state drives, and other electronic devices requiring fast and efficient data access.
Problems Solved: This technology addresses the need for reliable and high-speed memory systems that can efficiently read and write data while maintaining data integrity.
Benefits:
- Faster data access and retrieval
- Improved data storage efficiency
- Enhanced reliability and data integrity
Commercial Applications: Potential commercial applications include the manufacturing of computer memory modules, storage devices, and other electronic components requiring high-performance memory systems.
Prior Art: Prior art related to this technology may include patents or research papers on memory systems, cell arrays, and data storage technologies.
Frequently Updated Research: Researchers are constantly exploring new ways to improve memory systems, including increasing storage capacity, enhancing data transfer speeds, and reducing power consumption.
Questions about Memory Systems: 1. How does this memory system compare to traditional memory systems in terms of speed and efficiency? 2. What are the potential challenges in implementing this technology in real-world applications?
Original Abstract Submitted
A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.
