18553602. SUPERLATTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC simplified abstract (The Regents of the University of California)
Contents
SUPERLATTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC
Organization Name
The Regents of the University of California
Inventor(s)
Sayeef Salahuddin of Walnut Creek CA (US)
Suraj Singh Cheema of Berkeley CA (US)
Nirmaan Shanker of Berkeley CA (US)
Cheng-Hsiang Hsu of Berkeley CA (US)
SUPERLATTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC - A simplified explanation of the abstract
This abstract first appeared for US patent application 18553602 titled 'SUPERLATTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC
The patent application describes HfO—ZrO superlattice heterostructures integrated onto silicon transistors, stabilized with mixed ferroelectric-antiferroelectric order, and scaled down to approximately 20 Å.
- These gate stacks do not require scavenging of interfacial SiO, resulting in substantially lower leakage current and no mobility degradation.
- The HfO—ZrO multilayers with competing ferroelectric-antiferroelectric order provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO-based high-κ dielectrics.
Potential Applications:
- Advanced gate oxide stacks in electronic devices
- High-performance transistors
- Capacitors with large capacitance
Problems Solved:
- Lower leakage current and no mobility degradation
- Achieving large capacitance without scavenging interfacial SiO
Benefits:
- Enhanced performance of electronic devices
- Improved gate oxide thickness scaling
- Better control over gate leakage current
Commercial Applications:
- Semiconductor industry for high-performance transistors
- Electronics manufacturing for advanced gate oxide stacks
Prior Art: No specific prior art information provided in the abstract.
Frequently Updated Research: No information on frequently updated research relevant to this technology is included.
Questions about HfO—ZrO Superlattice Heterostructures: 1. How do these gate stacks achieve a large capacitance without scavenging interfacial SiO? 2. What are the potential implications of integrating these superlattice heterostructures onto silicon transistors for the semiconductor industry?
Original Abstract Submitted
Disclosed are HfO—ZrOsuperlattice heterostructures such as a gate stack (), stabilized with mixed ferroelectric-antiferroelectric order. directly integrated onto silicon (Si) transistors and scaled down to ˜20 Å. the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ˜6.5 Å effective SiOthickness, which is even smaller than the interfacial SiOthickness (8.0-8.5 Å) itself. and the resulting large capacitance cannot be achieved in conventional HfO-based high-κ dielectric gate stacks without scavenging the interfacial SiO. which has adverse effects on the electron transport and gate leakage current. Accordingly. the disclosed gate stacks (), which do not require such scavenging. provide substantially lower leakage current and no mobility degradation and demonstrate that HfO—ZrOmultilayers with competing ferroelectric-antiferroelectric order, stabilized in the sub-2 nm thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO-based high-κ dielectrics.
