18552213. PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING simplified abstract (Intel Corporation)
Contents
- 1 PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING
Organization Name
Inventor(s)
Xiaoning Ye of Portland OR (US)
Jorge A. Alvarez of Zapopan (MX)
Jose de Jesus Jauregui Ruelas of Guadalajara (MX)
Vijaya K. Kunda of Portland OR (US)
Hong-Yi Luoh of Portland OR (US)
PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18552213 titled 'PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING
Simplified Explanation
The abstract describes a patent application related to modifying signal lines in the pin field of a printed circuit board layout to improve signal integrity by reducing line impedance.
- Signal lines in the pin field are extended to optimize routing space between pads and adjacent signal lines.
- The extension of signal lines is a subtractive approach, where lines are extended to occupy available space and design rule violations are subtracted out.
- The edge of a signal line is extended to keep-out regions associated with pads in the pin field.
- The edge of the signal line is also extended to keep-out regions associated with a centerline that extends through a line of pads adjacent to the signal line.
Potential Applications
This technology can be applied in various industries where high signal integrity is crucial, such as telecommunications, aerospace, and consumer electronics.
Problems Solved
1. Reduced line impedance leading to improved signal integrity. 2. Optimal use of routing space between pads and adjacent signal lines.
Benefits
1. Enhanced signal integrity. 2. Improved performance of electronic devices. 3. Efficient use of available routing space.
Potential Commercial Applications
Optimizing signal lines in printed circuit board layouts can benefit companies involved in the manufacturing of electronic devices, especially those where signal integrity is a critical factor.
Possible Prior Art
Prior art related to optimizing signal lines in printed circuit board layouts may include research papers, patents, or industry standards focusing on signal integrity and impedance control in electronic circuits.
Unanswered Questions
How does this technology impact the overall cost of manufacturing electronic devices?
The abstract does not provide information on the cost implications of implementing this technology. It would be interesting to explore whether the benefits of improved signal integrity outweigh any potential increase in manufacturing costs.
Are there any limitations to the extension of signal lines in the pin field?
The abstract does not mention any potential limitations or challenges associated with extending signal lines in the pin field. Further research could investigate any constraints or drawbacks of this approach.
Original Abstract Submitted
Signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. The widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. The signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. The edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. The edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.
