18544110. Translation Lookaside Buffer Entry Locking (Apple Inc.)
Contents
Translation Lookaside Buffer Entry Locking
Organization Name
Inventor(s)
Brett S. Feero of Lake Oswego OR US
Brian T. Mokrzycki of Portland OR US
Jonathan Y. Tong of Austin TX US
Michael D. Snyder of Cedar Park TX US
James N. Hardage of Austin TX US
Translation Lookaside Buffer Entry Locking
This abstract first appeared for US patent application 18544110 titled 'Translation Lookaside Buffer Entry Locking
Original Abstract Submitted
Techniques are disclosed relating to using an instruction (e.g., a pre-translate instruction) to lock translations in TLB entries. The execution of the instruction may include storing translation information in a TLB entry, and setting an indication that the entry is locked. The processor circuitry may receive an invalidate command corresponding to the locked entry. Processor circuitry may, in response to the invalidate command and based on the indication that the entry is locked, maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command. Processor circuitry may be further configured to modify previously-stored data in a given entry to aggregate, in the entry, translation information for multiple regions of the second address space.
