18540544. TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN simplified abstract (Intel Corporation)
Contents
- 1 TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN
Organization Name
Inventor(s)
Willy Rachmady of Beaverton OR (US)
Cheng-Ying Huang of Portland OR (US)
Matthew V. Metz of Portland OR (US)
Nicholas G. Minutillo of Beaverton OR (US)
Sean T. Ma of Portland OR (US)
Anand S. Murthy of Portland OR (US)
Jack T. Kavalieros of Portland OR (US)
Tahir Ghani of Portland OR (US)
Gilbert Dewey of Beaverton OR (US)
TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN - A simplified explanation of the abstract
This abstract first appeared for US patent application 18540544 titled 'TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN
Simplified Explanation
The patent application describes a transistor structure with specific features for improved performance and efficiency.
- The transistor includes a semiconductor body with laterally opposed body sidewalls and a top surface.
- A gate structure contacts the top surface of the body.
- A source region contacts one of the body sidewalls, while a drain region contacts the other body sidewall.
- Isolation regions are located under the source and drain regions, with their top surfaces in contact with the bottom surfaces of the source and drain regions.
- The isolation regions play a crucial role in the transistor configuration, ensuring proper electrical isolation and performance.
Potential Applications
The technology described in the patent application could be applied in various electronic devices and systems, including:
- Integrated circuits
- Microprocessors
- Memory devices
- Power management systems
Problems Solved
The innovation addresses several challenges in transistor design and fabrication, such as:
- Improving electrical isolation between different regions of the transistor
- Enhancing overall performance and efficiency
- Reducing leakage currents and power consumption
Benefits
The technology offers the following benefits:
- Higher transistor performance
- Improved energy efficiency
- Enhanced reliability and longevity of electronic devices
Potential Commercial Applications
The technology has potential commercial applications in industries such as:
- Semiconductor manufacturing
- Electronics
- Telecommunications
- Automotive
Possible Prior Art
One possible prior art for this technology could be the development of FinFET transistor configurations, which also focus on improving transistor performance and efficiency.
Unanswered Questions
How does this technology compare to existing transistor designs in terms of performance and efficiency?
The article does not provide a direct comparison between this technology and existing transistor designs. Further research and testing would be needed to evaluate the performance differences.
What are the specific manufacturing processes required to implement this transistor structure?
The article does not delve into the detailed manufacturing processes involved in implementing this transistor structure. Additional information on fabrication techniques would be necessary for practical implementation.
Original Abstract Submitted
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
- Intel Corporation
- Willy Rachmady of Beaverton OR (US)
- Cheng-Ying Huang of Portland OR (US)
- Matthew V. Metz of Portland OR (US)
- Nicholas G. Minutillo of Beaverton OR (US)
- Sean T. Ma of Portland OR (US)
- Anand S. Murthy of Portland OR (US)
- Jack T. Kavalieros of Portland OR (US)
- Tahir Ghani of Portland OR (US)
- Gilbert Dewey of Beaverton OR (US)
- H01L29/06
- H01L29/08
- H01L29/10
- H01L29/205
- H01L29/423
- H01L29/78