18532245. ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY simplified abstract (Intel Corporation)

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

Organization Name

Intel Corporation

Inventor(s)

Abhishek Appu of El Dorado Hills CA (US)

Subramaniam Maiyuran of Gold River CA (US)

Mike Macpherson of Portland OR (US)

Fangwen Fu of Folsom CA (US)

Jiasheng Chen of El Dorado Hills CA (US)

Varghese George of Folsom CA (US)

Vasanth Ranganathan of El Dorado Hills CA (US)

Ashutosh Garg of Folsom CA (US)

Joydeep Ray of Folsom CA (US)

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18532245 titled 'ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

Simplified Explanation

Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

• Data aware sparsity via compressed bitstreams
• Block sparse dot product instructions
• Depth-wise adapter for a systolic array

Potential Applications

The technology described in this patent application could be applied in various fields such as:

• Artificial intelligence
• Machine learning
• Signal processing

Problems Solved

This technology helps in efficiently performing arithmetic operations on sparse data, which can be challenging using traditional methods. It addresses the following problems:

• Handling sparse data efficiently
• Improving processing speed for arithmetic operations

Benefits

The benefits of this technology include:

• Increased efficiency in processing sparse data
• Improved performance in arithmetic operations
• Enhanced capabilities for systolic processing units

Potential Commercial Applications

With its ability to handle sparse data efficiently, this technology could find applications in various industries such as:

• Data analytics
• Image and video processing
• Financial modeling

Possible Prior Art

One possible prior art in this field could be the use of parallel processing units for arithmetic operations on sparse data. However, the specific techniques described in this patent application may offer unique advantages over existing methods.

How does this technology compare to existing methods for processing sparse data?

This article provides an overview of the techniques described in the patent application, but it does not delve into a detailed comparison with existing methods.

What are the specific hardware requirements for implementing this technology?

While the abstract mentions software, firmware, and hardware logic, it does not provide specific details on the hardware requirements for deploying this technology.

Original Abstract Submitted

Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.