18524458. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
- 1 SEMICONDUCTOR MEMORY DEVICE
SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Hiroshi Maejima of Setagaya Tokyo (JP)
SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18524458 titled 'SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation
The semiconductor memory device described in the abstract utilizes different voltages to read data from memory strings efficiently. Here are some key points to explain the innovation:
- Memory cell array with memory strings, selection transistors
- Controller applies different voltages during read operation
- First voltage higher than ground to source line
- Second voltage to selected memory string gate lines
- Second voltage also to first selection gate lines of non-selected memory strings in first period
- Third voltage higher than ground and lower than second voltage to first selection gate lines of non-selected memory strings in second period
Potential Applications
The technology can be applied in various memory devices such as solid-state drives, smartphones, tablets, and other electronic devices requiring fast and efficient memory operations.
Problems Solved
This technology solves the problem of interference between selected and non-selected memory strings during read operations, leading to more accurate and reliable data retrieval.
Benefits
- Improved read operation efficiency
- Reduced interference between memory strings
- Enhanced data accuracy and reliability
Potential Commercial Applications
- Solid-state drives
- Mobile devices
- Embedded systems
- Data centers
Possible Prior Art
One possible prior art could be the use of different voltages in memory devices to improve read operation efficiency. However, the specific technique of applying different voltages to selected and non-selected memory strings during different periods of the read operation may be a novel aspect of this innovation.
Unanswered Questions
How does this technology impact power consumption in semiconductor memory devices?
The abstract does not provide information on the power consumption implications of this technology. It would be interesting to know if the use of different voltages during read operations has any significant impact on power efficiency.
Are there any limitations to the scalability of this technology in terms of memory array size?
It is not clear from the abstract whether there are any limitations to the scalability of this technology when applied to larger memory arrays. Understanding the potential constraints in scaling up this innovation could be crucial for its practical implementation in various memory devices.
Original Abstract Submitted
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
