18524094. SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF DIFFERENT STACKED CHIPS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF DIFFERENT STACKED CHIPS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Youngdeuk Kim of Suwon-si (KR)

SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF DIFFERENT STACKED CHIPS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18524094 titled 'SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF DIFFERENT STACKED CHIPS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

The semiconductor package described in the abstract consists of a first semiconductor chip with through electrodes, signal bonding pads, and dummy bonding pads, along with a second semiconductor chip stacked on top with chip pads corresponding to the bonding pads.

  • The first semiconductor chip includes through electrodes that penetrate the substrate, signal bonding pads electrically connected to the through electrodes, and dummy bonding pads electrically insulated from the through electrodes.
  • The second semiconductor chip has chip pads that correspond to the signal and dummy bonding pads of the first chip.
  • Conductive bumps connect the signal bonding pads of the first chip to the corresponding chip pads of the second chip, while separate conductive bumps connect the dummy bonding pads.
  • The conductive bumps consist of a signal bump pad and a solder bump for the signal connections, and a thermal bump pad and a solder bump for the dummy connections.

Potential Applications: - This technology can be used in advanced semiconductor packaging for improved electrical connections. - It can enhance the performance and reliability of stacked semiconductor chips in various electronic devices.

Problems Solved: - Provides a reliable and efficient method for connecting multiple semiconductor chips in a package. - Ensures proper signal transmission and thermal management within the package.

Benefits: - Improved electrical connectivity between stacked semiconductor chips. - Enhanced thermal dissipation for better performance and reliability of electronic devices.

Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Connectivity and Thermal Management This technology can be applied in the manufacturing of high-performance electronic devices such as smartphones, tablets, and computers to improve their overall functionality and reliability.

Prior Art: Further research can be conducted in the field of semiconductor packaging technologies to explore similar methods and advancements in the industry.

Frequently Updated Research: Stay updated on the latest developments in semiconductor packaging technologies to incorporate new innovations and improvements in future applications.

Questions about Semiconductor Packaging Technology: 1. How does this technology improve the electrical connections between stacked semiconductor chips? 2. What are the key advantages of using conductive bumps for signal and thermal connections in semiconductor packaging?


Original Abstract Submitted

A semiconductor package includes: a first semiconductor chip including a first substrate, first through electrodes, first signal bonding pads electrically connected to the first through electrodes, and first dummy bonding pads electrically insulated from the first through electrodes, wherein the first through electrodes penetrate the first substrate; a second semiconductor chip stacked on the first semiconductor chip and including a second substrate and a plurality of second chip pads on the second substrate and respectively corresponding to the first signal bonding pads and the first dummy bonding pads; first conductive bumps between the first signal bonding pads and the corresponding second chip pads; and second conductive bumps between the first dummy bonding pads and the corresponding second chip pads, wherein the first conductive bumps include a signal bump pad and a first solder bump, and the second conductive bumps include a thermal bump pad and a second solder bump.