18523314. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Hyunggyun Noh of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18523314 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application consists of a lower chip with a chip stacked structure on top. This structure includes multiple upper chips. An underfill layer is present between the lower chip and the chip stacked structure, as well as between the upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip features at least one lower trench on its upper surface, while at least one of the upper chips has at least one upper trench on its upper surface.
- The semiconductor package includes a lower chip with a chip stacked structure on top.
- The chip stacked structure comprises multiple upper chips.
- An underfill layer is positioned between the lower chip and the chip stacked structure, as well as between the upper chips.
- A molding layer surrounds the underfill layer and the chip stacked structure.
- The lower chip has at least one lower trench on its upper surface, while at least one of the upper chips has at least one upper trench on its upper surface.
Potential Applications: - This technology can be used in the manufacturing of advanced semiconductor devices. - It can be applied in the development of high-performance electronic products.
Problems Solved: - Provides a more efficient and reliable way to stack chips in semiconductor packages. - Helps improve the overall performance and durability of electronic devices.
Benefits: - Enhanced chip stacking capabilities. - Improved thermal management. - Increased reliability and longevity of electronic products.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Performance This technology can be utilized in the production of smartphones, tablets, laptops, and other consumer electronics to enhance their performance and reliability in a competitive market.
Prior Art: Readers can explore prior patents related to semiconductor packaging technology to gain a deeper understanding of the advancements in this field.
Frequently Updated Research: Stay updated on the latest research and developments in semiconductor packaging technology to leverage the most cutting-edge solutions for electronic devices.
Questions about Semiconductor Packaging Technology: 1. What are the key advantages of using a chip stacked structure in semiconductor packaging? 2. How does the presence of trenches on the upper and lower chips impact the overall performance of the semiconductor package?
Original Abstract Submitted
A semiconductor package includes a lower chip. A chip stacked structure is arranged on the lower chip. The chip stacked structure includes a plurality of upper chips. An underfill layer is disposed between the lower chip and the chip stacked structure and between the plurality of upper chips. A molding layer surrounds the underfill layer and the chip stacked structure. The lower chip has at least one lower trench positioned on an upper surface of the lower chip. At least one of the plurality of upper chips has at least one upper trench on an upper surface of the at least one of the plurality of upper chips.
