18522637. Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry simplified abstract (Micron Technology, Inc.)

Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry

Organization Name

Micron Technology, Inc.

Inventor(s)

Hung-Wei Liu of Meridian ID (US)

Vassil N. Antonov of Boise ID (US)

Ashonita A. Chavan of Boise ID (US)

Darwin Franseda Fan of Boise ID (US)

Jeffery B. Hull of Boise ID (US)

Anish A. Khandekar of Boise ID (US)

Masihhur R. Laskar of Boise ID (US)

Albert Liao of Boise ID (US)

Xue-Feng Lin of Boise ID (US)

Manuj Nahar of Boise ID (US)

Irina V. Vasilyeva of Boise ID (US)

Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry - A simplified explanation of the abstract

This abstract first appeared for US patent application 18522637 titled 'Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry

Simplified Explanation

The abstract describes a method of forming a vertical transistor with specific microwave annealing steps to reduce the concentration of elemental-form H in the channel region.

• The method involves multiple time-spaced microwave annealing steps.
• The annealing steps reduce the average concentration of elemental-form H in the channel region.
• The reduced concentration of elemental-form H is between 0.005 to less than 1 atomic percent.

Potential Applications

This technology could be applied in the semiconductor industry for the production of vertical transistors with improved performance and reliability.

Problems Solved

This method addresses the issue of high concentration of elemental-form H in the channel region of vertical transistors, which can negatively impact device performance.

Benefits

• Improved transistor performance.
• Enhanced reliability.
• Better control over elemental-form H concentration.

Potential Commercial Applications

Vertical transistors manufactured using this method could be used in various electronic devices such as smartphones, computers, and other consumer electronics.

Possible Prior Art

There may be prior art related to methods of reducing impurities in semiconductor devices using annealing processes, but specific examples would need to be researched.

How does this method compare to traditional annealing processes in terms of efficiency and cost-effectiveness?

This article does not provide a direct comparison between this method and traditional annealing processes in terms of efficiency and cost-effectiveness. Further research or experimentation would be needed to determine the advantages of this specific method.

What are the long-term effects of the reduced concentration of elemental-form H on the overall performance and lifespan of the vertical transistor?

The article does not address the long-term effects of the reduced concentration of elemental-form H on the performance and lifespan of the vertical transistor. Additional studies or testing would be required to assess the long-term implications of this method.

Original Abstract Submitted

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.