18522547. BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT simplified abstract (STMicroelectronics International N.V.)

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT

Organization Name

STMicroelectronics International N.V.

Inventor(s)

Promod Kumar of Greater Noida (IN)

Kedar Janardan Dhori of Ghaziabad (IN)

Harsh Rawat of Faridabad (IN)

Nitin Chawla of Noida (IN)

Manuj Ayodhyawasi of Noida (IN)

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18522547 titled 'BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT

Simplified Explanation

The memory array described in the patent application is designed for in-memory computation operations, where each memory cell stores weight data for the computation. The array includes row and column structures, with row controllers capable of simultaneously activating multiple word lines, and column processing circuits with discharge time sensing circuits for each column to monitor the time taken to discharge the bit line during computation. The analog signals generated by the sensing circuits are converted to digital signals for processing by computation circuitry, which then generates a decision output for the computation operation.

• Memory array for in-memory computation operations
• Row and column structures with word lines and bit lines
• Row controller for simultaneous activation of multiple word lines
• Column processing circuits with discharge time sensing circuits
• Conversion of analog signals to digital signals for processing
• Computation circuitry for generating decision output

Potential Applications

The technology described in the patent application could be applied in various fields such as artificial intelligence, machine learning, data analytics, and pattern recognition.

Problems Solved

This technology helps in improving the efficiency and speed of in-memory computation operations by enabling simultaneous activation of multiple word lines and monitoring the discharge time of bit lines.

Benefits

The benefits of this technology include faster computation speeds, reduced power consumption, and enhanced performance in in-memory computing tasks.

Potential Commercial Applications

One potential commercial application of this technology could be in the development of specialized hardware for deep learning and neural network applications.

Possible Prior Art

One possible prior art for this technology could be memory arrays used in traditional computing systems for storing and retrieving data.

How does this technology compare to existing in-memory computation solutions?

This technology offers the advantage of simultaneous activation of multiple word lines and real-time monitoring of bit line discharge times, potentially leading to faster and more efficient computation.

What are the scalability limitations of this memory array design?

The scalability of this memory array design may be limited by factors such as the complexity of the row and column structures, the number of memory cells that can be efficiently controlled, and the speed of the computation circuitry.

Original Abstract Submitted

A memory array includes memory cells arranged in rows and columns where each row includes a word line connected to memory cells of the row and each column includes a bit line connected to memory cells of the column. Each memory cell stores a bit of weight data for an in-memory computation operation. A row controller circuit coupled to the word lines through drive circuits is configured to simultaneously actuate multiple word lines during the in-memory computation operation. A column processing circuit includes a discharge time sensing circuit for each column that generates an analog signal indicative of a time taken during the in-memory computation operation to discharge the bit line from a precharge voltage to a threshold voltage. The analog signals are converted to digital signal and a computation circuitry performs digital signal processing calculations on the digital signals to generate a decision output for the in-memory computation operation.