18521600. Controller-Level Memory Repair simplified abstract (Micron Technology, Inc.)
Contents
- 1 Controller-Level Memory Repair
Controller-Level Memory Repair
Organization Name
Inventor(s)
Smruti Subhash Jhaveri of Boise ID (US)
Controller-Level Memory Repair - A simplified explanation of the abstract
This abstract first appeared for US patent application 18521600 titled 'Controller-Level Memory Repair
Simplified Explanation
The patent application describes a method and apparatus for sharing redundant memory portions at a controller-level to enable memory repair between multiple memory blocks. The controller can borrow spare rows from one memory die to repair faults in another memory die, thus increasing overall memory reliability.
- Memory dies can have multiple spare rows for repairing faulty bits.
- Controller inventories unrepaired faults and available spare rows across memory dies.
- Controller can borrow spare rows from one memory die to repair faults in another.
- Memory access requests can be remapped to spare rows for repair.
Potential Applications
This technology can be applied in various industries where reliable memory storage is crucial, such as data centers, telecommunications, and automotive systems.
Problems Solved
This technology solves the problem of memory faults in memory dies that cannot be repaired with available spare rows, thus increasing memory reliability and longevity.
Benefits
The benefits of this technology include improved memory repair capabilities, increased memory reliability, and extended lifespan of memory blocks.
Potential Commercial Applications
Potential commercial applications of this technology include memory modules for servers, networking equipment, and embedded systems, where reliable memory storage is essential for optimal performance.
Possible Prior Art
One possible prior art could be memory repair techniques using spare rows within a memory die itself, without the ability to borrow spare rows from other memory dies.
Unanswered Questions
How does this technology impact overall system performance?
This article does not delve into the potential impact of memory repair on the overall performance of the system. It would be interesting to know if there are any trade-offs in terms of speed or efficiency when utilizing this memory repair technique.
Are there any limitations to the number of spare rows that can be borrowed between memory dies?
The article does not address any potential limitations on the number of spare rows that can be borrowed between memory dies. It would be important to understand if there are any restrictions on the amount of memory repair that can be achieved using this method.
Original Abstract Submitted
Described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. Each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. If a memory die has more faults than spare rows, the memory die cannot repair the additional faults. This document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. The controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. The controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.
