18520189. Sharable Usage-Based Disturbance Circuitry simplified abstract (Micron Technology, Inc.)
Contents
- 1 Sharable Usage-Based Disturbance Circuitry
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Sharable Usage-Based Disturbance Circuitry - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Sharable Usage-Based Disturbance Circuitry
Organization Name
Inventor(s)
Kang-Yong Kim of Boise ID (US)
Sharable Usage-Based Disturbance Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 18520189 titled 'Sharable Usage-Based Disturbance Circuitry
Simplified Explanation
The patent application describes apparatuses and techniques for implementing shareable usage-based disturbance circuitry in memory devices. This circuitry helps manage disturbance across different sections of memory, making the memory device more efficient and cost-effective.
- Memory devices can have circuits that manage disturbance across multiple sections of memory.
- Shareable usage-based disturbance circuitry includes counter circuits and error-correction-code circuits.
- This circuitry helps reduce manufacturing costs, power consumption, and signal routing complexity.
- By sharing circuitry between sections, memory devices can be more efficient and cost-effective.
Potential Applications
The technology can be applied in various memory devices, such as solid-state drives, mobile devices, and servers.
Problems Solved
1. Mitigating usage-based disturbance in memory devices. 2. Reducing manufacturing costs and power consumption.
Benefits
1. Cost-effective memory devices. 2. Improved efficiency and performance. 3. Simplified signal routing.
Potential Commercial Applications
Optimizing memory devices for consumer electronics. SEO Optimized Title: Commercial Applications of Shareable Usage-Based Disturbance Circuitry Technology
Possible Prior Art
Prior art in memory devices includes dedicated circuits for managing disturbance within each memory section.
Unanswered Questions
1. How does the shareable usage-based disturbance circuitry impact the overall performance of the memory device? 2. Are there any limitations or drawbacks to implementing this technology in memory devices?
Original Abstract Submitted
Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.
