18518579. SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

SEMICONDUCTOR STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Sheng-Chih Lai of Hsinchu County (TW)

Chung-Te Lin of Tainan City (TW)

SEMICONDUCTOR STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18518579 titled 'SEMICONDUCTOR STRUCTURE

Simplified Explanation

The semiconductor structure described in the patent application includes memory cells stacked along a first direction, each consisting of a memory stack, connecting lines, and insulating layers. The memory stack comprises a first dielectric layer, a channel layer, a charge trapping layer, a second dielectric layer, and a gate layer. The connecting lines run along the first direction and cover the side surfaces of the memory stack, while the insulating layers are located beside the connecting lines and cover the side surfaces of the memory stack.

• Memory cells stacked along a first direction
• Memory stack composed of multiple layers including dielectric, channel, charge trapping, and gate layers
• Connecting lines covering side surfaces of the memory stack
• Insulating layers located beside connecting lines and covering side surfaces of the memory stack

Potential Applications

• Non-volatile memory devices
• Flash memory
• Solid-state drives

Problems Solved

• Increased memory density
• Improved data retention
• Enhanced performance of memory devices

Benefits

• Higher storage capacity
• Faster data access
• More reliable memory technology

Original Abstract Submitted

A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.