18516367. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Sungkeun Park of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18516367 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application consists of a first redistribution wiring layer with distinct regions, a semiconductor chip placed on one region, a sealing member covering the chip, vertical conductive wires passing through the sealing member, a second redistribution wiring layer on top of the sealing member with connections to the vertical wires, and bonding pads with unique patterns for bonding the vertical wires.
- The semiconductor package includes a unique layout of redistribution wiring layers to facilitate efficient electrical connections within the package.
- Vertical conductive wires pass through a sealing member, providing a compact and effective design for the package.
- The bonding pads feature concavo-convex patterns for secure bonding of the vertical wires, ensuring reliable connections.
- The design allows for improved electrical performance and reliability in semiconductor packaging applications.
- The innovative bonding pad patterns enhance the overall functionality and durability of the semiconductor package.
Potential Applications: This technology can be applied in various semiconductor packaging applications where compact design and reliable electrical connections are essential, such as in consumer electronics, automotive electronics, and industrial equipment.
Problems Solved: The technology addresses the need for efficient and reliable electrical connections in semiconductor packages, improving overall performance and reliability in electronic devices.
Benefits: - Enhanced electrical performance - Improved reliability - Compact design for space-saving applications - Secure bonding for long-lasting connections
Commercial Applications: This technology has significant commercial potential in industries requiring advanced semiconductor packaging solutions, such as consumer electronics manufacturers, automotive electronics companies, and industrial equipment producers.
Questions about Semiconductor Package Design: 1. How does the unique layout of redistribution wiring layers contribute to the efficiency of the semiconductor package? 2. What are the advantages of using concavo-convex patterns on bonding pads for connecting vertical conductive wires?
Original Abstract Submitted
A semiconductor package includes a first redistribution wiring layer having a first region and a second region surrounding the first region, a semiconductor chip disposed on the first region of the first redistribution wiring layer, a sealing member covering the semiconductor chip on the first redistribution wiring layer, vertical conductive wires penetrating the sealing member on the second region of the first redistribution wiring layer, a second redistribution wiring layer disposed on the sealing member and including second redistribution wirings electrically connected to the vertical conductive wires, and bonding pads provided on an upper surface of the first redistribution wiring layer or a lower surface of the second redistribution wiring layer, each bonding pad having a concavo-convex pattern on an upper surface of the bonding pad. The vertical conductive wires are bonded to the concavo-convex patterns of the bonding pads, respectively.
