18515797. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Junghoon Kang of Suwon-si (KR)
Unbyoung Kang of Suwon-si (KR)
Seungwan Shin of Suwon-si (KR)
Byoungwook Jang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18515797 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes a lower redistribution wiring layer with two regions, a semiconductor chip connected to the first region, a sealing member on the side surface of the chip and lower redistribution layer, vertical conductive structures on the second region, a marking pattern on the chip, seed layer pads on the vertical conductive structures, and an upper redistribution wiring layer.
- Lower redistribution wiring layer with two regions and first redistribution wirings
- Semiconductor chip on the first region, electrically connected to first redistribution wirings
- Sealing member on side surface of chip and lower redistribution wiring layer
- Vertical conductive structures on second region, electrically connected to first redistribution wirings
- Marking pattern on semiconductor chip
- Seed layer pads on vertical conductive structures
- Upper redistribution wiring layer with second redistribution wirings
Potential Applications: - Advanced semiconductor packaging technology - High-performance electronic devices - Integrated circuits
Problems Solved: - Improved electrical connectivity in semiconductor packages - Enhanced reliability and performance of electronic devices
Benefits: - Increased efficiency in semiconductor packaging - Enhanced signal transmission capabilities - Improved overall device performance
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for High-Performance Electronic Devices This technology can be utilized in various industries such as telecommunications, consumer electronics, automotive, and aerospace for the development of high-performance electronic devices with improved reliability and efficiency.
Questions about the technology: 1. How does the vertical conductive structures improve the electrical connectivity in the semiconductor package? 2. What are the potential market implications of implementing this advanced semiconductor packaging technology in various industries?
Original Abstract Submitted
A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings.
