18515536. THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Euntaek Jung of Seongnam-si (KR)

JoongShik Shin of Suwon-si (KR)

JiHye Yun of Hwaseong-si (KR)

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18515536 titled 'THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

Simplified Explanation

The abstract describes a 3D semiconductor memory device with a unique structure involving source and electrode patterns stacked on a horizontal semiconductor layer, along with a vertical semiconductor pattern penetrating both structures.

  • Source structure with first and second source conductive patterns stacked on horizontal semiconductor layer
  • Electrode structure with multiple electrodes stacked vertically on source structure
  • Vertical semiconductor pattern penetrating electrode and source structures, with sidewall in contact with source structure
  • Discontinuous interface in first source conductive pattern between horizontal semiconductor layer and second source conductive pattern

Potential Applications

  • High-density memory storage devices
  • Faster data processing in electronic devices
  • Improved performance in computing systems

Problems Solved

  • Increased memory capacity in smaller devices
  • Enhanced data transfer speeds
  • Better efficiency in semiconductor memory technology

Benefits

  • Higher storage capacity
  • Faster data access and retrieval
  • Improved overall performance of electronic devices


Original Abstract Submitted

A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.