18510919. SIGNAL PROCESSOR AND SIGNAL PROCESSING SYSTEM simplified abstract (Rohm Co., Ltd.)
Contents
SIGNAL PROCESSOR AND SIGNAL PROCESSING SYSTEM
Organization Name
Inventor(s)
Masanori Onodera of Kyoto-shi (JP)
SIGNAL PROCESSOR AND SIGNAL PROCESSING SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 18510919 titled 'SIGNAL PROCESSOR AND SIGNAL PROCESSING SYSTEM
Simplified Explanation
The present disclosure describes a signal processor with the ability to write data to a storage unit based on designated address maps.
- First terminal for inputting clock signal or data signal
- Second terminal for inputting clock signal or data signal
- Storage unit with address map for data writing permission and prohibition
- Designation unit to designate address maps
- Processing unit to write data to storage unit based on designated address map
- Potential Applications:**
- Data processing systems - Communication devices - Embedded systems
- Problems Solved:**
- Efficient data writing based on designated address maps - Improved signal processing capabilities
- Benefits:**
- Enhanced data processing efficiency - Flexibility in data writing permissions - Streamlined signal processing operations
- Potential Commercial Applications:**
- Semiconductor industry - Telecommunications sector - IoT devices market
- Possible Prior Art:**
There may be prior art related to signal processors with address map designation capabilities, but specific examples are not provided in this context.
- Unanswered Questions:**
- 1. How does the signal processor handle conflicts between multiple address maps when writing data?**
The abstract does not mention how the processor resolves conflicts if there are overlapping permissions or prohibitions in different address maps.
- 2. Are there any limitations to the size or complexity of the address maps that can be set in the storage unit?**
It is not clear from the abstract whether there are constraints on the address map configurations in terms of size or complexity.
Original Abstract Submitted
The present disclosure provides a signal processor (signal processing device). The signal processor includes: a first terminal, into which one of a clock signal and a data signal is input; a second terminal, into which another one of the clock signal and the data signal is input; a storage unit, in which an address map is set to define an address permitting data writing and an address prohibiting data writing; a designation unit, configured to designate the address map set in the storage unit; and a processing unit, configured to write a data based on the data signal to the storage unit according to the address map designated by the designation unit. The designation unit may designate a first address map and a second address map different from the first address map.
