18510732. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Woojin Lee of Hwaseong-si (KR)
Hoon Seok Seo of Suwon-si (KR)
Sanghoon Ahn of Hwaseong-si (KR)
Kyu-Hee Han of Hwaseong-si (KR)
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18510732 titled 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor device described in the abstract includes a substrate with an active pattern, a first interlayer dielectric layer with a recess, and a lower connection line that is electrically connected to the active pattern.
- The semiconductor device has a substrate with an active pattern.
- A first interlayer dielectric layer is on the substrate and includes a recess on its upper portion.
- A lower connection line in the first interlayer dielectric layer is electrically connected to the active pattern.
- The lower connection line includes a conductive pattern.
- The recess of the first interlayer dielectric layer selectively exposes the top surface of the conductive pattern.
- A barrier pattern is present between the conductive pattern and the first interlayer dielectric layer.
Potential Applications
- Integrated circuits
- Microprocessors
- Memory devices
Problems Solved
- Improved electrical connections in semiconductor devices
- Enhanced performance and reliability of electronic components
Benefits
- Increased efficiency in electronic devices
- Better signal transmission
- Reduced risk of electrical failures
Original Abstract Submitted
A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.
