18507621. SILICON CARBIDE WAFER AND SILICON CARBIDE SEMICONDUCTOR DEVICE INCLUDING THE SAME simplified abstract (DENSO CORPORATION)
Contents
SILICON CARBIDE WAFER AND SILICON CARBIDE SEMICONDUCTOR DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
HIDEYUKI Uehigashi of Nisshin-shi (JP)
SILICON CARBIDE WAFER AND SILICON CARBIDE SEMICONDUCTOR DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18507621 titled 'SILICON CARBIDE WAFER AND SILICON CARBIDE SEMICONDUCTOR DEVICE INCLUDING THE SAME
The abstract of the patent application describes a silicon carbide wafer with a substrate and an epitaxial layer made of silicon carbide. The epitaxial layer has a low trap density in the chip formation region, and the substrate has low Ti and Cr densities.
- The silicon carbide wafer includes a substrate and an epitaxial layer made of silicon carbide.
- The epitaxial layer has a trap density of 1.0×10cm or less in the chip formation region.
- The substrate has low Ti and Cr densities, measured by a SIMS method.
- The chip formation region is where a semiconductor element is formed, surrounded by an outer peripheral region.
- The trap density is derived by a DLTS method at an activation energy of 0.10 to 0.20 eV.
Potential Applications: - Power electronics - High-temperature applications - RF devices
Problems Solved: - Reduced trap density in the chip formation region - Improved performance and reliability of semiconductor devices
Benefits: - Enhanced efficiency of power electronics - Increased durability in high-temperature environments - Better signal integrity in RF devices
Commercial Applications: Title: "Advanced Silicon Carbide Wafers for High-Performance Electronics" This technology can be used in the production of high-performance electronic devices such as power modules, RF amplifiers, and sensors. The market implications include improved device performance, reliability, and longevity.
Questions about Silicon Carbide Wafer Technology: 1. How does the low trap density in the chip formation region impact the performance of semiconductor devices? 2. What are the advantages of using silicon carbide wafers in high-temperature applications?
Frequently Updated Research: Researchers are continually exploring ways to further reduce trap densities in silicon carbide wafers to enhance the performance of semiconductor devices. Stay updated on the latest advancements in epitaxial growth techniques and material characterization methods.
Original Abstract Submitted
A silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×10cmor less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×10cmor less measured by a SIMS method and a Cr density of 1.0×10cmor less measured by a SIMS method.
