18504745. CONTACT PLUGS AND METHODS FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

CONTACT PLUGS AND METHODS FORMING SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Kuo-Hua Pan of Hsinchu (TW)

Je-Wei Hsu of Hsinchu (TW)

Hua Feng Chen of Hsinchu (TW)

Jyun-Ming Lin of Hsinchu (TW)

Chen-Huang Peng of Hsinchu (TW)

Min-Yann Hsieh of Kaohsiung (TW)

Java Wu of Hsinchu (TW)

CONTACT PLUGS AND METHODS FORMING SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18504745 titled 'CONTACT PLUGS AND METHODS FORMING SAME

Simplified Explanation

The method described in the patent application involves the following steps:

• Forming a transistor with a dummy gate stack over a semiconductor region
• Forming an Inter-Layer Dielectric (ILD) covering a source/drain region
• Removing the dummy gate stack to create a trench in the ILD
• Forming a low-k gate spacer in the trench
• Forming a replacement gate dielectric extending into the trench
• Forming a metal layer to fill the trench
• Performing planarization to create a gate dielectric and a metal gate
• Forming a source region and a drain region on opposite sides of the metal gate

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1. 1. 1. Potential Applications

• Advanced semiconductor manufacturing processes
• High-performance electronic devices

1. 1. 1. Problems Solved

• Improving transistor performance
• Enhancing device reliability

1. 1. 1. Benefits

• Increased speed and efficiency of electronic devices
• Better control over transistor operation
• Potential for smaller and more powerful devices

Original Abstract Submitted

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.