18504093. MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT simplified abstract (Samsung Electronics Co., Ltd.)
Contents
MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
Organization Name
Inventor(s)
Daeseok Byeon of Seongnam-si (KR)
MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18504093 titled 'MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
Simplified Explanation
The memory device described in the patent application includes a memory cell array with a first memory block and a second memory block arranged adjacent to each other in a first direction. The device also includes driving signal lines corresponding to vertically stacked word lines, and a pass transistor circuit with an odd number of pass transistor groups connected between the driving signal lines and the memory cell array. One of the pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacent to the first pass transistor in a second direction.
- Memory device with memory cell array including first and second memory blocks
- Driving signal lines corresponding to vertically stacked word lines
- Pass transistor circuit with odd number of pass transistor groups
- First pass transistor connected between first word line of first memory block and first driving signal line
- Second pass transistor connected between first word line of second memory block and first driving signal line adjacent to first pass transistor
- Potential Applications
- Data storage devices - Computer memory systems - Mobile devices
- Problems Solved
- Efficient data storage and retrieval - Improved memory access speed - Enhanced memory cell array organization
- Benefits
- Higher memory density - Faster data access - Improved overall performance of memory devices
Original Abstract Submitted
A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
