18500311. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18500311 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application consists of a base chip, a first semiconductor chip with through-vias and bump structures, and multiple stacked second semiconductor chips with through-vias and adhesive layers.
- The first semiconductor chip is positioned on the base chip and is covered by an encapsulant, along with the plurality of second semiconductor chips.
- The adhesive layers on the second semiconductor chips have a width equal to or less than the width of the first semiconductor chip and each of the second semiconductor chips.
- The adhesive layers are parallel to the upper surface of the base chip, providing structural integrity to the stacked semiconductor chips.
- Key Features and Innovation:**
- Stacked semiconductor chips with through-vias and adhesive layers for improved connectivity and structural support.
- Encapsulant covering the semiconductor chips for protection and stability.
- Adhesive layers with specific width for optimal adhesion and alignment.
- Potential Applications:**
- This technology can be used in various electronic devices requiring compact and efficient semiconductor packaging.
- Suitable for applications in consumer electronics, telecommunications, automotive, and industrial sectors.
- Problems Solved:**
- Addresses the need for reliable and compact semiconductor packaging solutions.
- Enhances the structural integrity and connectivity of stacked semiconductor chips.
- Benefits:**
- Improved performance and reliability of electronic devices.
- Cost-effective and efficient semiconductor packaging solution.
- Enhanced durability and stability of semiconductor components.
- Commercial Applications:**
- Title: Advanced Semiconductor Packaging Technology for Enhanced Device Performance
- This technology can be utilized in the production of smartphones, tablets, IoT devices, and other electronic gadgets.
- Market implications include increased demand for high-performance and compact semiconductor packages in various industries.
- Questions about Semiconductor Packaging Technology:**
1. How does the adhesive layer width impact the overall performance of the semiconductor package? 2. What are the specific advantages of using through-vias in stacked semiconductor chips?
- Frequently Updated Research:**
Ongoing research focuses on optimizing the design and materials used in semiconductor packaging to further improve performance and reliability.
Original Abstract Submitted
A semiconductor package includes a base chip, a first semiconductor chip on the base chip, the first semiconductor chip including first through-vias, first bump structures on the first front surface of the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips including second through-vias, adhesive layers respectively on the second front surfaces of the plurality of second semiconductor chips, and an encapsulant between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips. The adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip.
