18494426. Memory System and Method for Use In the Memory System simplified abstract (Huawei Technologies Co., Ltd.)

Memory System and Method for Use In the Memory System

Organization Name

Huawei Technologies Co., Ltd.

Inventor(s)

Zvi Schneider of Hod Hasharon (IL)

Dor Shmoish of Hod Hasharon (IL)

Assaf Natanzon of Hod Hasharon (IL)

Memory System and Method for Use In the Memory System - A simplified explanation of the abstract

This abstract first appeared for US patent application 18494426 titled 'Memory System and Method for Use In the Memory System

Simplified Explanation

The memory controller in this patent application stores data blocks in a first memory tier by striping data on data drives of a first drive type, and then determines and stores parities for the data stripes in a second memory tier.

• Data blocks are stored in a first memory tier by striping data on data drives of a first drive type.
• The memory controller determines a first parity for at least one data stripe and stores it in one of the data drives of the first drive type.
• A plurality of second parities are determined for the data stripe and stored in a second memory tier.

• • Potential Applications:**

- Data storage systems - Cloud computing - Big data analytics

• • Problems Solved:**

- Efficient data storage and retrieval - Data protection and fault tolerance - Improved performance and reliability of memory systems

• • Benefits:**

- Enhanced data storage capacity - Increased data reliability and fault tolerance - Improved system performance and efficiency

Original Abstract Submitted

A memory controller stores data comprising a plurality of data blocks in a first memory tier by data striping data on data drives of a first drive type. The memory controller determines a first parity for at least one data stripe of a plurality of data stripes, stores the first parity in one of data drives of the first drive type, determines a plurality of second parities for the at least one data stripe of the plurality of data stripes, and stores the second parities in a second memory tier.